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- Acharya T.

Acharya T. - John Wiley & Sons, 2000. - 292 p.
ISBN 0-471-48422-9
Download (direct link): standardforImagecompressioncon2000.pdf
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— Register B: This is a special-purpose 8-bit register. The compressed bitstream is actually output from the B register as shown in the ‘ByteOutQ’ routine in the MQ-coder algorithm. There is a detector built with this register to determine whether all the bits of the register are l’s. If all the bits of the B register are 1, then the bit-stuffing operation is initiated by the controller.
— Register Q: This is just a 16-bit register to hold the probability estimation qe obtained by accessing the Q-table based on the Q-index supplied by the update logic circuitry from the info table.
• Adder: The adder computes the basic arithmetic steps of the MQ-coder algorithm. It is capable of addition (C + qe), subtraction (^4 — qe), and comparison (A — qe < qe) required in the MQ-coder algorithm. Since size of the registers C, A, and Q are 32 bits, 16 bits, and 16 bits respectively, the adder needs to be capable of computing 32-bit integer arithmetic operations.
• Control circuit: The control circuit generates control signals for all the registers and the tables. It is nothing but a state machine to generate the control signals during execution of the MQ-coder algorithm. The working principle of the state machine is similar to the controller in the EBCOT architecture. We avoid detailed discussion of the state machine here. The counter inputs the control circuit to control the B register to output the compressed bitstream. The counter is initialized by 12. As soon as the counter becomes 0 during the encoding process, the content of register B is output as the compressed bitstream and a new byte of data is loaded to B from register C.
• Q-table: The Q-table consists of 47 entries of Qr. values as shown in Table 7.7. The Q-table is addressed by the 6-bit Q-index. Depending on the Q-index, the corresponding Qe entry (probability estimation value qe) is read from the table and loaded into the 16-bit register Q, which is used by the adder to add it with C or subtract from A as shown in the “CodeLPSQ” or “CodeMPSQ” routines.
DECODER ARCHITECTURE FOR JPEG2000
245
9.5 DECODER ARCHITECTURE FOR JPEG2000
The tope-level architecture for the JPEG2000 decoder is shown in Figure 9.14. The architecture is similar to the encoder architecture shown in Figure 9.1 with data flow in the reverse direction.
bitstrrMm
Fig. 9.14 A top-level architecture for the JPEG2000 decoder.
The bitstream parsing module parses the compressed file to generate the code-stream. The code-stream is decoded by the three MQ-decoders (BAC1, BAC2, BAC3) in order to generate the context and data pairs corresponding to each subband. The MQ-decoder architecture is very similar to the encoder architecture with few minor changes. The code byte in the MQ-decoder is loaded into the B register and the decoder decodes it using the MQ-decoding algorithm. The basics of the modules of the decoder are functionally similar to the encoder. After the context and data are generated by the MQ-decoder, they are stored in the CXD buffers (CXD bufferl, CXD buffer2, and CXD buffer3). The EBCOT decoders decodes the context and data to generate the bit-planes of the code-blocks. The EBCOT decoder algorithm is essentially the same as the encoder algorithm with small and obvious changes in v and X memories and registers. For example, in the EBCOT decoder the data from v (value) and x (sign) are written into the subband memory instead of reading from it. We leave the details of the EBCOT architecture as an exercise for the reader. The data formatter circuits (DF1, DF2 and DF3) convert these sign-magnitude values of the code-blocks into two’s complement representation in order to be used by the inverse discrete wavelet transform (IDWT) architecture. The IDWT architecture generates the image tiles.
246 VLSI ARCHITECTURES FOR JPEG2000
9.6 SUMMARY OF OTHER ARCHITECTURES FOR JPEG2000
There are only a few other papers published in the literature discussing the VLSI architectures for the critical components in the JPEG2000 encoder and decoder, as of writing this book. The JPEG2000 algorithm is very intensive both in computation and in memory requirements. It is evident from the discussions in previous sections that the entropy encoding part of the JPEG2000 algorithm consumes a significant portion (more than 50%) of the total clock cycles required to compress an image. The bit-plane coding (EBCOT) consumes the highest computation time because of bit-wise processing in every bit-plane of the code-blocks. In EBCOT processing, an TV-bit element in a code-block is converted into N individual samples of 1 bit to be encoded. The memory organization of these bit-planes and access of the bits becomes very tricky in software implementation in a general-purpose computer or a digital signal processor (DSP) type media architecture. Special-purpose memory and register architectures have been proposed by Andra, Acharya and Chakrabarti [9, 5] in order to efficiently access the bit-planes of the code-blocks and encode each bit in each bit-plane. We have discussed this architecture in greater detail in previous sections in this chapter.
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