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- Acharya T.

Acharya T. - John Wiley & Sons, 2000. - 292 p.
ISBN 0-471-48422-9
Download (direct link): standardforImagecompressioncon2000.pdf
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35 23,3 + 25,3 RAl RS+2/2,8 = 22,8
36 - RAl RS-2/4,1 = 24,1
MEM1 consists of two banks and MEM2 consists of four banks. The multibank structure increases the memory bandwidth and helps support highly pipelined operation. Details of the memory organization and size, register file, and schedule for the overall architecture with specific details for each constituent filter have been included in [27].
REFERENCES 133
Total time required to transform an N x N block using (5, 3) wavelet filter using this architecture is 2[iV/2j + 3Ta + 2Ts + N + 5 + |_iV/2jN clock cycles, where Ta is delay of an adder and Ts is delay of a shifter. Any other type of wavelet filters can be efficiently executed in this architecture as well. Details of these filters and their timing for execution in this architecture have been presented in [27].
5.4 SUMMARY
In this chapter, we presented VLSI algorithms and architectures for discrete wavelet transforms. We described the traditional convolution (filtering) approach for computation of discrete wavelet transform and described how a systolic architecture can be designed for wavelet filters by exploiting the symmetric relationship of the filter coefficients. Since the lifting-based wavelet transform is a development of the late 1990s and is new in the VLSI community, we emphasized more on the VLSI architectures for the lifting-based DWT computation in this chapter. Lifting-based DWT has many advantages over the traditional convolution-based approach. It requires less memory and computation for implementation compared to the convolution-based approach. We reviewed and presented the VLSI architectures that have been reported very recently for lifting-based DWT. We presented how the data-dependency diagram for the lifting computation can be mapped into pipelined architectures for suitable VLSI implementation, and proposed enhancement of the pipeline architectures by applying different schemes reported in the literature. We described in greater detail a highly folded VLSI architecture for computation of both one-dimensional and two-dimensional transformations.
REFERENCES
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4. JPEG 2000 Final Committee Draft (FCD), “JPEG 2000 Committee Drafts,” http://www.jpeg.org/CDsl5444.htm.
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VLSI ARCHITECTURES FOR DISCRETE WAVELET TRANSFORMS
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14. M. D. Adams and F. Kossentini, “Reversible Integer-to-Integer Wavelet Transforms for Image Compression: Performance Evaluation and Analysis,” IEEE Trans, on Image Processing, Vol. 9, pp. 1010-1024, June 2000.
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